Date: 07/04/2018
By: Deltawabiyy
the frequency of the CPU’s clock source, or FOSC. The chips support multiple operating modes that can use different clock sources to conserve power when possible. Baud Rate Control Register BAUDCON The Baud Rate Control Register BAUDCON contains bits that relate to enhanced features of the chip’s bit-rate generator for serial communications. Bit 7 ABDOVF = 1 when a rollover has occurred while in auto-baud detect mode. Firmware must clear the bit. Bit 6 RCIDL = 1 when the receiver is idle no receive operation is in progress . Bit 5 RXDTP sets the polarity for received data as inverted 1 or non-inverted 0 . Bit 4 TXCKP sets the polarity for the idle state as low 1 or high 0 . Bit 3 BRG16 determines whether to use an eight 0 or sixteen 1 bit value to set the bit rate. In general, 16 bits enables greater accuracy in selecting rates. Bit 2 is unimplemented and reads zero. Bit 1 WUE is set to 1 to cause the EUSART to trigger an interrupt on a falling edge at RX. The interrupt can wake the chip from Sleep mode. 234 Ports for Embedded Systems Bit 0 ADBDEN is set to 1 to cause the chip to detect the bit rate on the next received byte. The received byte must equal 55h for accurate detecting of the rate. Oscillator Control Register OSCCON In the oscillator control register OSCCON , the SCS1 and SCS0 bits select the CPU’s clock source. In normal, full-power operation, the clock source is the primary clock specified in CONFIG1H. For reduced power consumption, the clock source can be the Timerl oscillator or the internal oscillator block. When using the internal oscillator block, the IRCF2..IRCF0 bits select the frequency. When using the Timer1 oscillator, the frequency is determined by the clock source connected to the TlOSI and TlOSO pins. After changing the clock source, firmware that wants to continue using the serial port will likely need to change the values in the SPBRG and SPBRGH registers as described below. Oscillator Tuning Register OSC prom-electric.ru
